Researchers Rethink the Transistor at a Material Level

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Transistors are reaching their physical limits in size and speed. As transistors are made smaller, the distance between the source and drain decreases, leading to high leakage currents. And as the transistor size approaches the atomic level, it is difficult to control the current flow, leading to a higher probability of computation errors.

Smaller transistors mean slower switching speeds, which is especially problematic in newer applications like artificial Intelligence, where massive datasets need to be processed. Denser integration also becomes a challenge because of stacking and thermal management issues.

This article discusses recent research developments that push the boundaries of existing transistor technologies and how they may outperform current devices.

Wood-based transistor
Below, we'll discuss a wood-based transistor developed by researchers at Linköping University and the KTH Royal Institute of Technology, among other transistor research breakthroughs. Image courtesy of Thor Balkhed/Linköping University

Growing 2D Materials on a Silicon CMOS Wafer

Current transistors are bulky and cannot be easily stacked vertically for high density. For such integration, transistors must be made of ultrathin 2D materials, which are only a few atoms thick. However, growing 2D materials on a silicon wafer is challenging because it usually requires a temperature of around 600°C—and circuits can only withstand up to 400°C.

To tackle these issues, Massachusetts Institute of Technology (MIT) researchers have developed a low-temperature process to grow 2D materials on-chip without damaging them. The new process reduces the time it takes to create the 2D materials and creates a uniform layer over the entire surface area. As a result, the new process can be used for larger surfaces than conventional processes.

Graduate student Jiadi Zhu holding the wafer developed with the new process
Graduate student Jiadi Zhu holding the wafer developed with the new process. Image courtesy of MIT

The MIT researchers focused on molybdenum disulfide, a transparent and flexible material with electronic and photonic properties, for demonstrating and validating their new process. Their process is placed in an oven with two chambers: a low-temperature region in the front and a high-temperature region in the back. The wafer is placed in front so it remains intact. Vaporized molybdenum and sulfur precursors are pumped into the furnace. Molybdenum stays in the front, and sulfur precursor flows in the high-temperature region to decompose. After decomposition, it flows back to the low-temperature chamber, where the molybdenum disulfide grows.

The researchers placed the wafer vertically in the front chamber so neither edge was too close to the high-temperature region. They also deposited a thin layer of passivation material on top of the chip to prevent the sulfurization of metals like aluminum and copper, commonly used in silicon circuits for connecting a package or carrier. The passivation layer is later removed to make connections. The researchers plan to fine-tune their technique and explore the application of this process for flexible surfaces like polymers, textiles, and papers.